system type : generic-loongson-machine machine : Unknown processor : 0 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 874.96 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 1 VCED exceptions : not available VCEI exceptions : not available processor : 1 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 2 VCED exceptions : not available VCEI exceptions : not available processor : 2 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 3 VCED exceptions : not available VCEI exceptions : not available processor : 3 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 4 VCED exceptions : not available VCEI exceptions : not available processor : 4 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 5 VCED exceptions : not available VCEI exceptions : not available processor : 5 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 6 VCED exceptions : not available VCEI exceptions : not available processor : 6 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 0 core : 7 VCED exceptions : not available VCEI exceptions : not available processor : 7 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 0 VCED exceptions : not available VCEI exceptions : not available processor : 8 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 1 VCED exceptions : not available VCEI exceptions : not available processor : 9 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 2 VCED exceptions : not available VCEI exceptions : not available processor : 10 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 3 VCED exceptions : not available VCEI exceptions : not available processor : 11 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 4 VCED exceptions : not available VCEI exceptions : not available processor : 12 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 5 VCED exceptions : not available VCEI exceptions : not available processor : 13 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 6 VCED exceptions : not available VCEI exceptions : not available processor : 14 cpu model : ICT Loongson-3B V0.7 FPU V0.1 BogoMIPS : 880.43 wait instruction : no microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips64r1 ASEs implemented : shadow register sets : 1 kscratch registers : 0 package : 1 core : 7 VCED exceptions : not available VCEI exceptions : not available